1. Field of the Invention
The present invention generally relates to a data processing apparatus including a memory unit with ECC (Error-Correcting Code). More particularly, the invention is directed to a storage device equipped with a RAS (Reliability, Availability, Serviceability) circuit for easily diagnosing operating conditions in the memory unit and an ECC checking circuit.
2. Description of the Prior Art
FIG. 1 is a circuit diagram of the conventional diagnostic system for the storage device disclosed, e.g., in Japanese patent publication No. 60-37934. In the drawing, reference numeral 1 indicates a memory unit, reference numeral 2 denotes an address register, reference numeral 3 represents an output data register, reference numeral 4 is an ECC (Error-Correcting Code) checking circuit unit, reference numeral 5 denotes a memory control unit, reference numeral 6 indicates an error detecting control unit, reference numeral 7 represents an error detecting unit, reference numeral 8 is a Hamming code register, and reference numeral 9 indicates a work register. Furthermore, reference numerals 10 to 12 indicate holding registers and reference numerals 13 through 16 represent detecting registers.
Operations of the prior art diagnostic system for storage devices will be described. The memory unit 1 stores various sorts of data utilized in the data processing apparatus. Error-correcting code (referred to as simply "ECC") is given to the data stored in the memory unit 1. The address register 2 functions in such a manner that addresses of the memory unit 1 are set, and several pieces of the data relating to the addresses set in the address register 2 are written into and read from the address register 2. The output register 3 temporarily stores the data read from the memory unit 1.
The ECC checking circuit unit 4 firstly detects one(1)-bit error if one-bit error is contained in the data read from the memory unit 1, secondly corrects the above-described 1-bit error, and thirdly detects two-bit error when it is contained in the data. The ECC checking circuit unit 4 includes, as illustrated in FIG. 2, a Hamming code checking circuit 4-1, an error decoding circuit 4-2, and a 1-bit/2-bit error detecting circuit 4-3. These circuits are known in the art. The output data read from the memory unit 1 and then set in the output data register 3 is inputted to EOR (exclusive OR) circuits 4-1a, b, . . . , as illustrated in FIG. 2 to perform the normal Hamming code checking. Hamming code check outputs derived from these EOR circuits 4-1g and 4-1h are processed in OR circuits 4-2e, 4-2f, . . . . If there is the 1-bit error, then an error correcting code is calculated and transmitted to the error correcting circuit for performing error correction. The Hamming code check output is also inputted to the OR circuits 4-3a and 4-3b of the 1-bit/2-bit error detecting circuit 4-3. To an open collector OR circuit 4-3e of the 1-bit/2-bit error detecting circuit 4-3, outputs derived from the, open collector OR circuit 4-2e, 4-2f, . . . , 4-2g of the error decoding circuit 4-2 are supplied. The open collector OR circuit 4-3e outputs "1" when the 1-bit error is contained in the data, whereas open collector OR circuit 4-3f outputs "1" when the 2-bit error is contained therein.
The memory control unit 5 generates a 2-bit control signal is response to a test pattern stored in the memory unit 1 when the storage device is under diagnosis. The control signal "00" is produced from the memory control unit 5 when the normal test pattern containing no error is stored in the memory unit 1, the control signal "10" is derived therefrom when the 1-bit error pattern containing the 1-bit error is stored, and the control signal "01" is output therefrom in case that the 2-bit error pattern having the 2-bit error is stored therein.
The error detecting control unit 6, on the other hand, includes EOR (exclusive OR) circuits 6-1 and 6-2. The control unit 6 outputs "0" only when the ECC checking circuit 4 is under normal operation with respect to the diagnostic patterns stored in the memory unit 1 (will be described later). The error detecting unit 7 is constructed of latches 7-1 and 7-2, and an 0R circuit 7-3, and outputs an error announcing signal in case that a signal representative of incorrect operation of the ECC checking circuit 4 is supplied from the error detecting control unit 6 thereto.
The Hamming check code derived from the above-described Hamming code checking circuit 4-1 is temporarily set in the Hamming code register 8. The work register 9 functions as a register for setting the conditions of the major part of the ECC checking circuit unit 4. The holding register 10 temporarily sets the output data from the output data register 3, whereas the holding registers 11 and 12 temporarily set the address data of the address register 2. The detecting registers 13 to 16 work as registers for temporarily setting contents of the respective Hamming code register 8, work register 9 and holding registers 10 and 12. Accordingly, the detecting registers 13 to 16 examine the contents of the respective detecting registers 13 to 16 to analyze the cause of the error when the error detecting signal is derived from the error detecting unit 7. The other prior art technique in this field will be described with reference to FIGS. 3 and 4.
In FIG. 3, a storage device includes a bus 21, a DRAM (dynamic RAM) memory unit 22, and ECC checking circuit 23, a memory device/ECC circuit control unit 24, an input data line 25, a check-bit input data line 26, an output data line 27 for the DRAM memory unit, and a check-bit output data line 28. In this figure, reference numeral 29 represents a status signal for ECC checking circuit, reference numeral 30 indicates a control signal for ECC checking circuit, reference numeral 31 indicates an R(read)/W(write) signal, reference numeral 32 is a response signal, reference numeral 33 indicates an address line, reference numeral 34 denotes DRAM memory address line, and reference numeral 35 indicates an R/W signal for memory unit.
FIG. 4 is an internal circuit diagram of the memory unit/checking circuit control unit 24 shown in FIG. 3. In the figure, reference numeral 36 represents a 1-bit error detecting signal 29 (a portion of the status signal for ECC checking circuit), reference numeral 37 indicates a status signal for a refresh operation, reference numeral 38 is a write signal for DRAM memory unit (corresponding to the write signal for memory unit R/W signal 35), reference numeral 39 represents a memory write signal (corresponding to the write signal for R/W signal 31), reference numeral 40 denotes an operation cycle control circuit for memory unit, reference numerals 41A and 41B indicate AND circuits, reference numerals 42A and 42B represent OR circuits, and furthermore, reference numeral 43 is a memory read signal (corresponding to the read signal for R/W signal 31).
Operations of the storage device shown in FIGS. 3 and 4 will now be described.
First, the data stored in the DRAM memory unit 22 is read in response to the read signal of the R/W signal 31 via the bus 21.
When the above-described read signal and address 33 are inputted into the memory unit/ECC checking circuit control unit 24 (equivalent to Intel's DRAM controller 8207), this control unit 24 transmits the memory unit R/W signal 35 and the DRAM memory unit address 34 to the DRAM memory unit 22 (with error-correcting code). As a result, the data which the address indicates is supplied to the ECC checking circuit 23 through the output data line 27 for DRAM memory unit 27 and the output data line 28 for check bit (ECC bit). Thereafter, the error detection on the input data is caried out by the ECC checking circuit 23 (equivalent to Intel's Error Detection and Correction unit 8206) by utilizing the check bit. If there is one-bit error contained in the input data, the status signal for ECC checking circuit 29 is transmitted to the memory unit/ECC checking circuit control unit 24, in which this one-bit error is corrected. Then, the error-corrected input data and the response signal 32 are transmitted to the bus 21. The memory unit/ECC checking circuit control unit 24 transmits the ECC checking circuit control signal 30 to the ECC checking circuit 23. Subsequently, the ECC checking circuit 23 produces the check bit for the correcting data and delivers this check bit to the check-bit input data line 26. The memory unit/ECC checking circuit control unit 24 also supplies the write signal 35 by which both the correcting data existing in the input data line 25 and the check bit data present in the check bit input data line 26 are written into corresponding addresses of DRAM memory unit 22. The operation of this storage device is accomplished when the writing of the data is completed.
When the 1-bit error is not contained, then the data is transmitted to the bus 21.
As previously described, since a DRAM (dynamic RAM) element is employed as the memory unit in the DRAM memory unit 22, this memory element must be refreshed. The aim of the refreshing is to prevent the data stored in the memory unit from being depleted. In the refresh cycle of the memory unit, row address (RA) and column address (CA) are produced. Accordingly, the memory unit can be read. In case of memory capacity; of 2 Mbytes several tens of seconds are required to read the entire memory region within the refresh cycle. It is, of course, to correct the data and also to re-write it when the 1-bit error is contained in the data during the reading operation.
The theory of the write signal generation in case of the 1-bit error will now be described. When the DRAM element is refreshed, both the refreshing status signal 37 and the 1-bit error detecting signal 36 are supplied to the AND circuit 41a. If the 1-bit error is detected, the output signal of the AND circuit 41A is input to the OR circuits 42A and 42B, so that the write signal 38 for DRAM memory unit is generated and the internal operation cycle is prolonged by the operation cycle control circuit for memory unit 40.
During the reading operation, both the memory read signal 43 and the 1-bit error detecting signal 36 are inputted to the AND circuit 41B. The output of the AND circuit 41B is supplied to the OR circuits 42A and 42B when the 1-bit error occurs, with the result that the write signal for DRAM memory unit 38 is generated and the internal operation cycle is prolonged by the operation cycle control circuit for memory unit 40.
During the writing operation, the memory write signal is inputted into the OR circuit 42A so that the write signal 38 may be generated. The contents and operation of the above-mentioned microprocessor are disclosed, for example, in "Microsystem Components Handbook Microprocessors and Peripherals Vol. II (published by Intel, Santa Clara, Calif.)".
The following drawbacks are however involved in the above-described conventional storage devices.
In the first conventional storage device shown in FIGS. 1 and 2, when the 1-bit error diagnostic data is processed, the ECC checking circuit is operated under the normal condition even if one bit data other than the 1-bit error diagnostic data is detected by this checking circuit. Since the diagnostic data is once written in the memory unit and then is read for diagnosing the ECC checking circuit, this memory unit must be operated in the normal condition.
Moreover, upon occurrence of the bit error the storage device must be diagnosed, so that the overall system is necessarily interrupted every time the bit error occurs, and thus, the operating efficiency of the overall system is lowered.
Also in the second conventional storage device shown in FIGS. 3 and 4, if the 1-bit error occurs when the continuous reading operation of the memory unit is performed, the data is re-written after it has been corrected. As a result, the processing speed of the storage device is not only lowered considerably, but also complex control logic is required for the rewrite operation.